Beginning in 1985, several European and North American companies banded together to form the Joint Test Action Group (JTAG). The stated task was to solve the problem of printed-circuit board (PCB) manufacturing test, which was growing more difficult as integrated circuits (ICs) became smaller and more complex. The solution was eventually standardized as the IEEE Standard 1149.1-1990 Test Access Port and Boundary-Scan Architecture, which is hereby incorporated herein in its entirety by reference. This industry standard provides for inclusion of required test resources into ICs.
Boundary-scan builds on the concepts of in-circuit test. In boundary scan, physical probes (“nails”) which are placed mid-net in probe test technology, are replaced by boundary-scan cells (BSCs). These “virtual” probes are placed on-chip at IC inputs and IC outputs (the boundary of the IC), and are therefore placed at the net ends. The use of boundary scan testing results in two major improvements: (1) physical access is no longer required at boundary-scan nets, and (2) continuity test is no longer subject to IC complexity. The result is that the goal of manufacturing test, to isolate defects to a pin or net, can be accomplished by highly automated test-pattern generation (ATPG).
To provide a means to arbitrarily control and observe these BSCs with minimal pin overhead, the BSCs were designed to be serially chained to form a shift register between two IC pins, Test Data Input (TDI) and Test Data Output (TDO). Additional control structures required to select between normal and test operational modes were also been designed to minimize pin overhead and to maximize flexibility to handle test modes in addition to tests used for PCB manufacturing test. The Test Access Port (TAP) is based on a state machine (TAP Controller) that operates synchronously to a Test Clock (TCK, to which all operations of the test logic are synchronous) and under the control of a single Test Mode Select (TMS). The TAP Controller explicitly provides for a single instruction register that controls the test modes and for any number of test data registers (including the boundary-scan register) that are selected by specific instructions.
Standardization of the TAP and TAP Controller, as well as the boundary-scan architecture, has been key to the broad acceptance of the technology across IC, tester, and computer-automated engineering (CAE) tool vendors. This structured design-for-test (DFT) technique is used widely across all types of board designs by all sorts of board manufacturers, even those where catalog ICs and off-the-shelf testers and tools are used. Additionally, the flexibility of the TAP and TAP Controller allows access to other test features built into chip, board, or system, such as on-chip scan test or built-in self-test (BIST).
Rapid integration has placed more functionality from separate integrated circuits onto one integrated circuit or modules containing multiple integrated circuits. The integrated circuits and modules have become enormously complex. The increased complexity makes thorough testing of all functionality using scans at the boundary of such devices difficult, if not impossible. However, thorough testing is essential. For example, with automotive devices, failures can have severe safety consequences. In automotive devices it is important that high test-coverage is achieved for both static and dynamic faults, while still keeping the test-cost under control to meet the stringent safety standards.
However, the presence of modules containing random resistant faults that impact the controllability and observability of the test make the requirement to thoroughly test challenging. In addition, digital analysis cannot test random access memory (RAM) or analog modules. The inputs and outputs of RAM are not deterministic, and analog modules have either non-digital inputs or outputs. Solutions to mitigate these issues are usage of control/observe test-point insertion around these untestable modules to improve controllability and observability of the test.